FUNCTIONAL
DESCRIPTION
The
PCI-DIO-48/48S, PCI-DIO-48J/48JS, PCI-DIO-48JP/JPS, PCI-DIO-48JPL/JPLS,
PCI-DIO-48H/HS and PCI-DIO-24S are 24- and 48-bit parallel
digital input/output cards designed for use in PCI-Bus computers.
The card is 6.9 inches (175 mm) long and may be installed
in any 5-volt PCI slot in IBM and compatible computers.
The
48J/48JS cards use a 68-pin SCSI-type connector, while the
48H/48HS cards use a 100-pin SCSI-type connector. The 48JP/48JPS
cards use a 68-pin SCSI-type connector which is pin-in-socket,
and has jack-screws provided as a means to retain the mating
cable. The 48JPL/48JPLS cards use the 68-pin SCSI-type pin-in-socket
connectors; however one-touch latches are used instead of
jack screws. The 48/48S cards use 50-pin headers on the
face of the board, as well as the 24S card which is simply
a depopulated 48S card.
The
cards contain two Programmable Peripheral Interface chips
type 8255-5 (PPI) to provide computer interface to the 48
I/O lines. Each PPI provides three 8-bit ports A, B and
C. Each 8-bit port can be software configured to function
as either inputs or latched outputs. Port C can also be
configured with four inputs and four output latches.
Each
I/O line is buffered and capable of sourcing 15 mA or sinking
24 mA (64 mA on request). Tristate I/O line buffers are
configured automatically by the hardware logic for input
or output use according to a direction control signal from
the control register in the PPI. Pull-ups on the card assure
that there are no erroneous outputs at power up until the
card is initialized by system software.
These
cards use one address space, and occupy 16 consecutive register
locations. When the card is first installed, Windows 95/98/NT
will detect it as new hardware and assign it an IRQ number
and base address. There are no switches to set or base addresses
to assign, making it easy to use. You cannot set or change
the card's base address, you can only determine what the
system has assigned. The PCI Bus supports 64K of I/O address
space so your card's address may be located anywhere in
the 0000 to FFFF range.
INTERRUPTS
The
distinguishing feature for the "48S" model is
that the state of all inputs can be monitored and if one
or more of the bits change states, a latched interrupt request
can be generated. Therefore it is not necessary to use software
polling on the inputs to detect a change of state condition.
The change-of-state interrupt is enabled by a software write
command to an interrupt-enable register. Once latched, the
change-of-state interrupt can be cleared by a software write.
The
C3 bit on either 24-bit port can be used as an external
interrupt to the computer if interrupt enable (IEN) jumpers
are installed. When C3 is level triggered, an interrupt
is requested. Interrupts from the two ports are OR'ed together
with any change-of-state interrupt. The interrupts are assigned
by the system.
